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GHz PLL with I2C Bus and Four Chip Addresses
Preliminary Data Features
q
SDA 3302 Family
Bipolar IC
1-chip system for MPU control (I2C bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability Charge pump output with switch off option Up to 3*) high current band switch outputs (20 mA) Up to 4*) output ports (5 mA) P-DIP-18-5 P-DSO-20-1
q q
q q q
*) depending on version
P-DSO-16-1
Type SDA 3302-5 SDA 3302-5X SDA 3302-5X6 SDA 3302-5X SDA 3302-5X6
Ordering Code Q67000-H5112 Q67000-H5111 Q67000-H5110 Q67006-H5111 Q67006-H5110
Package P-DIP-18-5 P-DSO-20-1 (SMD) P-DSO-16-1 (SMD) P-DSO-20-1 Tape & Reel (SMD) P-DSO-16-1 Tape & Reel (SMD)
Semiconductor Group
1
02.97
SDA 3302 Family
Functional Description Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with PLL frequency-synthesis tuning. The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The crystal oscillator generates a sinusoidal signal suppressing the higher-order harmonics, which reduces the moire noise considerably. Circuit Description Tuning Section (refer to block diagram) UHF/VHF REF The tuner signal is capacitively coupled at the UHF/VHF input and subsequently amplified. The reference input REF should be decoupled to ground using a capacitor of low series inductance. The signal passes through an asynchronous divider with a fixed ratio of P = 8, an adjustable divider with ratio N = 256 through 32767 and is then compared in a digital phase/frequency detector to a reference frequency fREF of 7.8125 kHz. The latter is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q1, Q2), whose output signal is divided by Q = 512. The phase detector has two outputs UP and DOWN that drive the two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. PD, UD When the two signals are in phase, the charge-pump output (PD) goes highimpedance (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier an external transistor at the UD output and an external RC circuitry). The charge-pump output can also be set to high-impedance state when control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. UD can be disconnected internally by the control bit OS to enable external adjustments. By means of a control bit 5I the pump current can be switched between two values by software. This switchover permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains in the different TV bands can be compensated for example.
Q1, Q2
Semiconductor Group
2
SDA 3302 Family
Circuit Description (cont'd) P0-P2 P4-P7 The software-switched outputs (P0, P1, P2) can be used for direct band selection (20-mA current output). P4, P5, P6 and P7 are open-collector outputs for a variety of different purposes. The test bit T1 = 1 switches the test signals f REF (4 MHz/512) and Cy (divided input signal) to P6 and P7. Four different chip addresses can be set by appropriate connection of pin CAS.
CAS
I2C-Bus Interface SCL, SDA Data are exchanged between the processor and the PLL on the I2C bus. The clock is produced by the processor (input SCL), while pin SDA works as an input or output depending on the direction of the data (open collector; external pullup resistor). Both inputs have hysteresis and a lowpass characteristic, which enhances the noise immunity of the I2C bus. The data from the processor are applied to an I2C bus controller and filed in registers according to their function. When the bus is free, both lines are in the marking state (SDA, SCL are high). Each telegram begins with a start condition and ends with the stop condition. Start condition: SDA goes low while SCL remains high; stop condition: SDA goes high while SCL remains high. All further data exchanges occur while SCL is low and are accepted by the controller with the positive clock edge. For what follows, refer to the table of logic allocations. All telegrams are transmitted byte by byte, followed by a ninth clock pulse, during which the controller puts the SDA line on low (acknowledge condition). The first byte consists of seven address bits, with which the processor selects the PLL from a number of peripheral devices (chip select). The eighth bit is always low. In the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information follows. In each case the byte following the first byte must be of the same data type (or a stop condition).
VS, GND
When the supply voltage is applied, a power-on reset circuit prevents the PLL from putting the SDA line on low, which would block the bus.
Semiconductor Group
3
SDA 3302 Family
Circuit Description (cont'd) Logic Allocations
MSB A = Acknowledge
Address byte Prog. divider byte 1 Prog. divider byte 2 Control info. byte 1 Control info. byte 2
1 0 n7 1 P7
1 n14 n6 5I P6
0 n13 n5 T1 P5
0 n12 n4 T0 P4
0 n11 n3 1 X
MA1 n10 n2 1 P2
MA0 n9 n1 1 P1
0 n8 n0 OS P0
A A A A A
Divider Ratio N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 + + 128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 Band Selection P2-P0 = 1 Port Outputs P7-P4 = 1 Open-collector output is active. Open-collector output is active.
Pump Current Switchover 5I = 1 High current. UD Disable OS = 1 Test Mode T1, T0 = 0,0 T1 = 1 T0 = 1
VD is disabled.
Normal mode P6 = fREF; P7 = Cy Tristate charge pump PD is in high-impedance.
Semiconductor Group
4
SDA 3302 Family
Circuit Description (cont'd) Chip-Address Switching MA1 0 0 1 1 MA0 0 1 0 1 Voltage on CAS (0-0.1) VS open (0.4-0.6) VS (0.9-1) VS
Pulse Diagram Telegram Examples Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-CW1-Stop Start-Addr-CW1-CW2-DR1-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop Start-Addr-DR1-Stop Start Addr DR1 DR2 CW1 CW2 Stop = start condition = address = divider ratio 1st byte = divider ratio 2nd byte = control word 1st byte = control word 2nd byte = stop condition
Semiconductor Group
5
SDA 3302 Family
Pin Configuration (SDA 3302-5) (top view)
P-DIP-18-5
Semiconductor Group
6
SDA 3302 Family
Pin Definitions and Functions (SDA 3302-5) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol PD Q1 Q2 SDA SCL P7 P6 P5 P4 CAS P2 P1 P0 Function Active-filter input/charge-pump output Crystal Crystal Data input/output for I2C bus Clock input for I2C bus Port output (open collector) Port output (open collector) Port output (open collector) Port output (open collector) Chip-address switchover Port output (open collector) Port output (open collector) Port output (open collector) Supply voltage Signal input Amplifier reference input Ground Output active filter
VS
UHF/VHF REF GND UD
Semiconductor Group
7
SDA 3302 Family
Pin Configuration (SDA 3302-5X) (top view)
P-DSO-20-1
Semiconductor Group
8
SDA 3302 Family
Pin Definitions and Functions (SDA 3302-5X) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol PD Q1 Q2 N.C. SDA SCL P7 N.C. P6 P5 P4 CAS P2 P1 P0 Function Active-filter input/charge-pump output Crystal Crystal Not connected Data input/output for I2C bus Clock input for I2C bus Port output (open collector) Not connected Port output (open collector) Port output (open collector) Port output (open collector) Chip-address switchover Port output (open collector) Port output (open collector) Port output (open collector) Supply voltage Signal input Amplifier reference input Ground Active-filter output
VS
UHF/VHF REF GND UD
Semiconductor Group
9
SDA 3302 Family
Pin Configuration (SDA 3302-5X6) (top view)
P-DSO-16-1
Semiconductor Group
10
SDA 3302 Family
Pin Definitions and Functions (SDA 3302-5X6) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PD Q1 Q2 SDA SCL P7 P6 P5 P4 CAS P1 Function Active-filter input/output pump output Crystal Crystal Data input/output for I2C bus Clock input for I2C bus Port output (open collector) Port output (open collector) Port output (open collector) Port output (open collector) Chip-address switchover Port output (open collector) Supply voltage Signal input Amplifier reference input Ground Output active filter
VS
UHF/VHF REF GND UD
Semiconductor Group
11
SDA 3302 Family
Pin Definitions and Functions, Reference List SDA 3302 P-DIP-18-5 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SDA 3302X P-DSO-20-1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SDA 3302X6 Symbol P-DSO-16-1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PD Q1 Q2 N.C. SDA SCL P7 N.C. P6 P5 P4 CAS P2 P1 P0 Function
Input active-filter input charge pump output Crystal Crystal Not connected Data input/output for I2C bus Clock input for I2C bus Port output (open collector) Not connected Port output (open collector) Port output (open collector) Port output (open collector) Chip-address switchover Port output (open collector) Port output (open collector) Port output (open collector) Supply voltage Signal input Amplifier reference input Ground Output active filter
VS
UHF/VHF REF GND UD
Semiconductor Group
12
SDA 3302 Family
Block Diagram SDA 3302-5
Pin nos. refer to P-DIP-18 package only. For other packages, see reference list on page 16
Semiconductor Group
13
SDA 3302 Family
Absolute Maximum Ratings TA = 25 C Parameter Symbol 2) Limit Values min. Supply voltage Output PD Crystal Q1 Crystal Q2 Bus input/output SDA Bus input SCL Port output P7, P6, P5, P4 Chip-address switchover Port output P2, P1, P0 Signal input UHF/VHF Reference input REF Output active filter UD Bus output SDA Port output P7, P6, P5, P4 Port output P2, P1, P0 Chip temperature Total port output current Storage temperature Thermal resistance (system-air) max. 6 V V V V V V V V V V V V mA mA mA C mA C K/W open collector open collector open collector open collector for VS = 0 V for VS = 0 V Unit Remarks
VS V1 V2 V3 V4 V5 V6, 7, 8, 9 V10 V11, 12, 13 V15 V16 V18 I4L
- 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -1
VS VS VS
6 6 16
VS
16 0.3 0.3
VS
5 5 20 125 25
I6L, 7L, 8L, 9L - 1 I11L, 12L, 13L - 1 TC ZIL Tstg RthSA
- 40
125 80
2) Pin nos. refer to P-DIP-18 package
Semiconductor Group
14
SDA 3302 Family
Absolute Maximum Ratings TA = 25 C Parameter Symbol 2) Limit Values min. Operating Range Supply voltage Ambient temperature Input frequency Crystal frequency Programmable divider factor max. Unit Remarks
VS TA f15 f2, 3 N
4.5 - 20 16
5.5 80 1300 4
V C MHz MHz
256
32767
1) Design note: no 100 % final inspection. 2) Pin nos. refer to P-DIP-18 package
Semiconductor Group
15
SDA 3302 Family
Characteristics VS = 5 V; TA = 25 C Parameter Symbol 2) min. Current consumption Crystal-oscillator frequency Oscillator level1) (Voltage across crystal) Margin from 1st 1) and 2nd harmonic Input Sensitivity UHF/VHF Limit Values typ. 35 max. mA Unit Test Condition Test Circuit 1 1
IS f2, 3
VS = 5 V
series capacitance 18 pF; fxtal = 4 MHz
3.99975 4.000 4.00025 MHz
V2, 3
2.6
Vpp
20
dB
a15 a15 a15
- 27/10 - 27/10 - 27/10
3/315 3/315 3/315
3)
f15 = 70-500 MHz 2 f15 = 1000 MHz 2 f15 = 1100 MHz 2
Band-Select Outputs P0-P2 (switch with open collector) Reserve current Residual voltage
I13H V13L
10 0.5
A V
V13H = 13.5 V I13H = 20 mA
3 3
Port Outputs P4-P7 (switch with open collector) Reserve current Residual voltage
I9H V9L
10 0.5
A V
V9H = 13.5 V I9L = 1.7 mA
4 4
Note: The sum of the currents in ports P0-P7 must not exceed 25 mA
Phase-Detector Output PD Pump current Pump current Output voltage
I1H I1H V1L
90 22 1.0
230 300 50 75 2.5
A A V
5I = HIGH; V1 = 2 V 5I = LOW;
V1 = 2 V
locked
1) Design note: no 100 % final inspection. 2) Pin nos. refer to P-DIP-18 package 3) dBm/mVrms into 50
Semiconductor Group
16
SDA 3302 Family
Characteristics (cont'd) VS = 5 V; TA = 25 C Parameter Symbol 2) min. Output Active Filter UD (T0 = 1) Output current Output voltage Output voltage - I18 500 100 500 A mV mV Limit Values typ. max. Unit Test Condition Test Circuit
V18 = 0.8 V; IIH = 90 A V1L = 0 V
OS = 1
5 5 5
V18 V18
Chip-Address Switchover Input current Input current
I10H - I10H
50 50
A A
V10H = 5 V V10H = 0 V
7 7
Bus Inputs SCL, SDA Input voltage Input current Input current
V5H V5L I5H
- I5L
3
5.5 5.5 10 20
V V A A
6 6
V5H = VS V5L = 0 V
6 6
Output SDA (open collector) Reverse current Output voltage Edges SCL, SDA Rise time Fall time Shift Clock SCL Frequency H-pulse width L-pulse width
I4H V4L
10 0.4
A V
V4H = 5.5 V I4L = 3 mA
6 6
tR tF
1 0.3
s s
6 6
f5 t5H t5L
0 4 4.7
100
kHz s s
6 6 6
2) Pin nos. refer to P-DIP-18 package
Semiconductor Group
17
SDA 3302 Family
Characteristics (cont'd) VS = 5 V; TA = 25 C Parameter Symbol 2) min. Start Setup time Hold time Stop Setup time Bus free Data Exchange Setup time Hold time Input hysteresis1) SCL, SDA Lowpass cutoff1) frequency SCL, SDA
1) Design note: no 100 % final inspection. 2) Pin nos. refer to P-DIP-18 package
Limit Values typ. max.
Unit
Test Condition
Test Circuit
tSUSta tHDSta
4.7 4
s s
6 6
tSUsto tBUF
4.7 4.7
s s
6 6
tSUDat tHDDat
0.25 0 300 500
s s mV kHz
6 6
Semiconductor Group
18
SDA 3302 Family
Test Circuit 1
Semiconductor Group
19
SDA 3302 Family
Test Circuit 2
Test Circuit 3 Semiconductor Group 20
SDA 3302 Family
Test Circuit 4
Test Circuit 5 Semiconductor Group 21
SDA 3302 Family
I2C Bus Timing Diagram
Test Circuit 6
Test Circuit 7 Semiconductor Group 22
SDA 3302 Family
Application Circuit Semiconductor Group 23
SDA 3302 Family
Application Circuit
Calculation of Loop Filter Loop bandwidth R = (Ip x KVCO) / (C1 x P x N) Attenuation: = 0.5 x R x R x C1
P = prescaler N = programmable divider Ip = pump current KVCO = tuner slope R, C1 = loop filter
Example for channel 47:
P = 8, N = 11520, Ip = 100 A; KVCO = 18.7 MHz/V, R = 22 k, C1 = 180 nF, R = 336 Hz, fr = 54 Hz, = 0.67
Standard dimensioning: C2 = C1/5 Note: The high-impedance port outputs and CAS can be blocked against external noise with a capacitor of 1 nF.
Semiconductor Group
24
SDA 3302 Family
Input Sensitivity
I2C Bus Noise Immunity
The sinusoidal noise pulses are applied via a coupling capacitance of 33 pF to SCL and SDA inputs. Semiconductor Group 25
SDA 3302 Family
Package Outlines Plastic-Package, P-DIP-18-5 (Plastic Dual In-Line Package)
Plastic-Package, P-DSO-20-1 (SMD) (Plastic Dual Small Outline Package)
Semiconductor Group
26
GPS05094
GPD05586
SDA 3302 Family
Plastic-Package, P-DSO-16-1 (SMD) (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 27 Dimensions in mm
GPS05119

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